Hongwu Jiang （姜泓吾）

Assistant Professor
Microelectronics, Function Hub, HKUST(GZ)
Email: hongwujiang@hkust-gz.edu.cn

I am an Assistant Professor in the Microelectronics Thrust (Function Hub) at the Hong Kong University of Science and Technology (Guangzhou). I obtained my Ph.D. degree from Georgia Institute of Technology in 2022, where I was advised by Prof. Shimeng Yu. My research interests are in circuit and architecture design for efficient computing systems with CMOS and beyond CMOS technologies. To date, I have published more than 20 papers in leading conferences (VLSI, DAC, ISSCC, etc.) and journals (IEEE TCAS-I, IEEE T-Computer, JSSC, TCAD, etc.).

Openings

I’m looking for self-motivated Ph.D. students (Fall 2024) , and postdoctoral scholars to join our lab at MICS, Function Hub, HKUST(GZ). We also offer RA positions. Please email me your resume and other support material if you are interested.

Work Experience

  • Assistant Professor
    HKUST, GZ. Start from Jan, 2023
  • Research Intern
    IMEC, US. Summer 2021
  • Research Assistant
    ASU, Tempe. 2015 -- 2018

Education

  • Ph.D. in Electrical and Computer Engineering
    advised by Prof. Shimeng Yu
    Georgia Institute of Technology, 2019 -- 2022
  • M.S. in Electrical Engineering
    Arizona State University, 2012 -- 2014
  • B.S. in Automation
    Dalian University of Technology, 2008 -- 2012

Research Interests

Our research focuses on the design and application exploration of cutting-edge technologies in mixed-signal and digital circuit and system.

  • Compute-in-Memory chip design with robustness and scalability

  • Energy/Time-efficient hardware for edge computing (on-device learning, smart sensing, intelligent transportation, etc.)

  • VLSI design with emerging technologies (3D integration, cryogenic CMOS, machine learning aided design, etc.)

  • Software-hardware co-design for AI applications

    • Publications

    Book/Book chapters

    1. H. Jiang, S. Huang, S. Yu, “Compute-in-memory architecture”, Handbook of Computer Architecture, A. Chattopadhyay (Ed.), Publisher: Springer, 2023.

    Conferences

    1. H. Jiang, W. Li, S. Huang, S. Yu, “A 40nm analog-input ADC-free compute-in-memory RRAM macro with pulse-width modulation between sub-arrays,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2022, Hawaii, USA, highlight paper.
    2. W. Li, J. Read, H. Jiang , S. Yu, “A 40nm RRAM compute-in-memory macro with parallelism-preserving ECC for iso-accuracy voltage scaling,” IEEE European Solid-State Circuits Conference (ESSCIRC) 2022, Milan, Italy.
    3. W. Li, X. Sun, H. Jiang, S. Huang, S. Yu, “A 40nm RRAM compute-in-memory macro featuring on-chip write-verify and offset-cancelling ADC references,” IEEE European Solid-State Circuits Conference (ESSCIRC) 2021, virtual.
    4. W. Li, S. Huang, X. Sun, H. Jiang, S. Yu, “Secure-RRAM: A 40nm 16kb compute-in-memory macro with reconfigurability, sparsity control, and embedded security,” IEEE Custom Integrated Circuits Conference (CICC) 2021, virtual.
    5. S. Huang, X. Peng, H. Jiang, Y. Luo, S. Yu, “Exploiting process variations to protect machine learning inference engine from chip cloning,” IEEE International Symposium on Circuits and Systems (ISCAS) 2021, virtual.
    6. A. Lu, X. Peng, W. Li, H. Jiang, S. Yu, “NeuroSim validation with 40nm RRAM compute-in-memory macro,” IEEE International Conference on Artificial Intelligence Circuits & Systems (AICAS) 2021, virtual.
    7. S. Huang, H. Jiang, S. Yu, “Mitigating adversarial attack for compute-in-memory accelerator utilizing on-chip finetune,” IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) 2021, virtual.
    8. J-W. Su, X. Si, Y-C. Chou, T-W. Chang, W-H. Huang, Y-N. Tu, R. Liu, P-J. Lu, T-W. Liu, J-H. Wang, Z. Zhang, H. Jiang, S. Huang, S. Yu, K-T. Tang, C-C. Hsieh, R-S. Liu, S-H. Li, S-S. Sheu, H-Y. Lee, S-C. Chang, M-F. Chang, “A 28nm 64Kb inference-training two-way transpose multibit 6T SRAM computing-in-memory macro for AI edge chips” IEEE International Solid-State Circuits Conference (ISSCC) 2020, San Francisco, USA.
    9. H. Jiang, S. Huang, X. Peng, J.-W. Su, Y.-C. Chou, W.-H. Huang, T.-W. Liu, R. Liu, M.-F. Chang, S. Yu, “A two-way SRAM array based accelerator for deep neural network on-chip training,” ACM/IEEE Design Automation Conference (DAC) 2020, virtual (nomination for the best paper).
    10. S. Huang, X. Sun, X. Peng, H. Jiang, S. Yu, “Overcoming challenges for achieving high in-situ training accuracy with emerging memories,” IEEE/ACM Design, Automation & Test in Europe (DATE) 2020, virtual, invited.
    11. S. Huang, H. Jiang, X. Peng, W. Li, S. Yu, “XOR-CIM: Compute-in-memory SRAM architecture with embedded XOR encryption,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2020, virtual.
    12. W. Shim, H. Jiang, X. Peng, S. Yu, “Architectural design of 3D NAND Flash based compute-in-memory for inference engine,” ACM/IEEE International Symposium on Memory Systems (MEMSYS) 2020, virtual.
    13. H. Jiang, X. Peng, S. Huang, S. Yu, “MINT: Mixed-precision RRAM-based in-memory training architecture,” IEEE International Symposium on Circuits and Systems (ISCAS) 2020, virtual
    14. H. Jiang, R. Liu, S. Yu, “8T XNOR-SRAM based parallel compute-in-memory for deep neural network accelerator,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) 2020, virtual, invited.
    15. H. Jiang, X. Peng, S. Huang, S. Yu, “CIMAT: A transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training,” ACM/IEEE International Symposium on Memory Systems (MEMSYS) 2019, Washington, DC, USA.

    Journals

    1. H. Jiang, S. Huang, W. Li and S. Yu, "ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays," IEEE Transactions on Circuits and Systems I: Regular Papers, 2022.
    2. W. Li, X. Sun, S. Huang, H. Jiang, S. Yu, “A 40nm MLC-RRAM compute-in-memory macro with sparsity control, on-chip write-verify, and temperature-independent ADC references,” IEEE Journal of Solid State Circuits, vol. 57, no. 9, pp. 2868-2877, 2022.
    3. H. Jiang, W. Li, S. Huang, S. Cosemans, F. Catthoor, S. Yu, “Analog-to-digital converter design exploration for compute-in-memory accelerators,” IEEE Design & Test, vol. 39, no. 2, pp, 48-55, 2022.
    4. S. Huang, X. Sun, X. Peng, H. Jiang, S. Yu, “Achieving high in-situ training accuracy and energy efficiency with analog non-volatile synaptic devices,” ACM Transactions on Design Automation of Electronic Systems, vol. 27, no. 4, p. 37, 2022.
    5. J.-W. Su, X. Si, Y.-C. Chou, T.-W. Chang, W.-H. Huang, Y.-N. Tu, R. Liu, P.-J. Lu, T.-W. Liu, J.-H. Wang, Y.-L. Chung, J.-S. Ren, H. Jiang, S. Huang, S.-H. Li, S.-S. Sheu, C.-I. Wu, C.-C. Lo, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, S. Yu, M.-F. Chang, “Two-way transpose multibit 6T SRAM computing-in-memory macro for inference-training AI edge chips,” IEEE Journal of Solid-State Circuits, vol. 57, no. 2, pp. 609-624, 2022.
    6. S. Yu, H. Jiang, S. Huang, X. Peng, A. Lu, “Compute-in-memory chips for deep learning: recent trends and prospects”, IEEE Circuits and Systems Magazine, vol. 21, no. 3, pp. 31-56, 2021.
    7. X. Peng, S. Huang, H. Jiang, A. Lu, S. Yu, “DNN+NeuroSim V2.0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training,” IEEE Trans. CAD, vol. 40, no. 11, pp. 2306-2319, 2021.
    8. S. Huang, H. Jiang, X. Peng, W. Li, S. Yu, “Secure XOR-CIM engine: Compute-in-memory SRAM architecture with embedded XOR encryption,” IEEE Trans. VLSI Systems, vol. 29, no. 12, pp. 2027-2039, 2021.
    9. H. Jiang, X. Peng, S. Huang, S. Yu, “CIMAT: A compute-in-memory architecture for on-chip training based on transpose SRAM arrays,” IEEE Transactions on Computers, vol. 69, no. 7, pp. 944-954, 2020.

    People

    Ruihao He, Ph.D. student, 2023.9 - present

    Shaoxuan Li, Ph.D. student, 2023.9 - present

    Xipeng Lin, Ph.D. student, 2023.9 - present

    Teaching

    Memory Device Technologies and Circuit Design, Fall 2023

    Advanced VLSI Design, Spring 2024